The invention relates to an integrated circuit with a subordinate test interface, and to a method for transmitting digital data, in particular a method for transmitting test data to a test interface.
Modern microprocessor chips, including SoCs (System on Chip) may include at least one central control and processing unit, a Central Processing Unit or CPU “Core”, and a memory area of a size of several MB on one chip. On such a chip, a complex software program and data to be processed, which are executed or processed by the microprocessor, may thus be stored in the memory area. Such chips are, for instance, used in the automotive field in control devices so as to control e.g., engines.
During the development of the programs running on such a chip, and during the tests of the entire chip in the production environment, the software program is tested in combination with the environment of the chip, e.g., the connected sensors and actuators. Particular situations are caused in the chip to test the reaction of the chip.
Several hardware and software systems are known by which chips can be tested. Due to the increasing complexity entailed by the progressing development of chips it is no longer sufficient to observe the behavior of a chip at the pins thereof only. Instead, it has turned out that it is necessary to be able to specifically write test data in the chip memory area, and to read them out alike so as to be able to write test scenarios quickly and directly in the interior of the chip and to directly “observe” the processing of the corresponding data.
For direct write and read accesses to the memory area of a chip, the chip may, for instance, include a test interface which a plurality of own external contacts, i.e. pins, at the chip are assigned to.
Such a test interface is, for instance a JTAG module that will be referred to by way of example in the following in order to explain the invention. An exact specification of this interface is determined in IEEE 1149.
The JTAG standard defines a test interface, a TAP (Test Access Port) with a TAP controller that processes the test data. For the test interface, four signal lines are defined pursuant to the JTAG standard. A first signal line serves to transmit a test clock signal TCK (TCK=TestClocK), and via the second signal line TMS (TMS=TestModeSelect) a test mode signal is transmitted. Via two further signal lines TDI (TDI=TestDataIn) and TDO (TDO=TestDataOut), test data are supplied to the controller or read from it via the signal line TDO, respectively. By an optional fifth signal line, a test reset signal TRST (TRST=TestReSeT) may be transmitted additionally.
The thus specified interface has the disadvantage that at least four pins are required which are not used in the productive operation, i.e. in the actual working mode of the chip. Since these additional pins that are not used during the productive operation of the chip create costs and require space, it has been a permanent object of further developments to keep the number of pins necessary for the debugging of chips as small as possible.
As a solution, it has been suggested to multiplex the JTAG test pins with other pins that are used in the productive operation, so that no additional pins at the chip package have to be used for the implementation of the JTAG test interface. This solution, however, has the disadvantage that the function of the pins used for multiplexing can, during the use of the pins as JTAG test interface, not be tested therewith.
U.S. Pat. No. 6,088,822 thus describes a chip with a JTAG TAP controller which includes the functions specified in the standard, but is also connected with a data adapter on the chip. The data adapter connects the TAP controller with further logic function blocks on the chip. Optionally, in a first operating mode, the TAP controller may thus be operated pursuant to the JTAG standard, or, in a second operating mode, data from outside may, via the TAP controller and the data adapter, be written in the logic function blocks that are attainable via the data adapter, or be read out therefrom. In this variant, it is thus not just the pins of the TAP controller, but also the TAP controller itself that is used for another function not provided in the JTAG standard.
US 2001/0034598 discloses as an alternative solution the time multiplexing of the signals to be transmitted via the different signal lines. The data to be transmitted are successively transmitted via one line, so that, instead of the four—or optionally five—signal lines only one signal line and thus one pin is required for transmitting the information to the JTAG TAP controller. This solution thus reduces the number of pins required for a JTAG test interface.
Modern integrated circuits, in particular modern SoCs, however, often include more than one CPU core. Usually, one respective JTAG test interface is provided for each CPU core, which entails a corresponding number of pins. The JTAG test interfaces thus indeed enable the testing of the CPU cores, but the chip includes an undesired high number of pins for the JTAG test interfaces.
Another disadvantage of a JTAG-compliant test interface is the definition of the TAP controller as a finite state machine, wherein the host computer that is connected externally to the test interface is defined as master, and the chip to be tested is defined as slave. The host computer assumes that the chip or the TAP controller, respectively, of the JTAG test interface is always in the state defined by the TMS signal. A feedback of the chip about its actual state is not provided for. An undesired changing of the chip to another state due to interference will thus not be discovered and can often only be changed by a reboot with a reset of the TAP controller to a defined initial state.
Another disadvantage of the standard results from the specification that the data to be sent to the TAP controller have to be signalized such that a signal edge must have reached the TAP controller after half a clock duration at the latest. This strongly restricts the maximum signal propagation delay on one line and thus the maximally possible length of the data line with a predetermined clock rate.
Meanwhile, however, the JTAG standard has the advantage that there exist already many software programs for host computers by which a chip can be tested via a JTAG TAP controller. Due to the variety of applications developed for the JTAG standard it is therefore useful to maintain the standard to the required extent to be able to further utilize the existing programs.
For these and other reasons, there is a need for the present invention.